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ordering number : enn6976a 82102tn (ot) / 83101rm (ot) no. 6976-1/29 overview the LC72151V is a pll frequency synthesizer for car audio systems. it can implement high-performance multifunction tuners such as rds tuners and features a fast locking circuit. functions ? high-speed programmable divider fmin: 10 to 160 mhz: pulse swallower type amin: 2 to 40 mhz: pulse swallower type 0.5 to 10 mhz: direct division type ? if counter hctr: 0.4 to 25 mhz: for fm if count lctr: 10 to 500 khz: for am if count 1.0 to 20 10 3 hz: for frequency measurement ? reference frequency one of 11 frequencies may be selected (when a 10.25 or 10.35 mhz crystal is used) 50, 30 * , 25, 12.5, 10, 9 * , 6.25, 5, 3.125, 3 * , 1 khz note: cannot be used when a 10.25 mhz crystal is used ? phase comparator supports dead band control built-in unlock detection circuit built-in deadlock clearing circuit ? built-in amplifier for forming an active low-pass filter built-in operational amplifier for fm high-speed locking built-in mos transistor for am tuning ? built-in crystal oscillator output buffer ? i/o ports general-purpose i/o: 2 pins four input ports (maximum) three output ports (maximum) ? serial data i/o supports communication with the controller in the ccb format. ? operating ranges supply voltage: 4.5 to 5.5 v (v dd ) 7.5 to 9.5 v (av dd ) operating temperature: C40 to +85c ? package ssop30 package dimensions unit: mm 3191a-ssop30 15 1 16 30 9.75 0.5 7.6 5.6 0.1 (1.3) 1.5max 0.65 (0.43) 0.22 0.15 sanyo: ssop30 [LC72151V] LC72151V sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan pll frequency synthesizer for electronic tuning in car audio systems cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyos original bus format and all the bus addresses are controlled by sanyo.
no. 6976- 2 /29 LC72151V pin assignment lc72 151 (top view) v xi n do xo u t i/o - 1 i/o - 2 s 1 30 2 3 4 5 6 7 8 9 10 11 12 29 28 27 26 25 24 23 22 21 20 xb u f o-3 v dd v ss fm in am in av dd av ss ao u t 1 cl ao u t 2 pd m 2 pd f pd m 1 ain 2 pd s tgi1 tgo tgi2 ain 1 13 14 + 15 19 18 17 16 hct r/ i - 3 l c tr /i- 4 di ce ar ef s s av ss
no. 6976- 3 /29 LC72151V block diagram pd s pd f a v dd a v ss a out 1 a in 1 a re f pd m 1 am in hct r/ i - 3 v dd v ss tg i2 fm in xo u t xin uni v e r s a l cou n t e r f a s t l o ck up con t rol unl ock de t e ct or re f e re nce di v i de r ph ase d e tec t o r cha rg e p u m p d a ta sh ift r e g i ste r la t c h 1 2 b i t s pr o g r a m m abl e di v i de r swal l o w c o u n ter 1/ 16, 1 / 17 4b it s po wer on r eset ccb i/f pd s tg i1 c l d o i/o - 1 i/o - 2 cha rg e p u m p fo r fast l o c k tg o ce di o- 3 pd m 2 a out 2 a in 2 lc t r / i - 4 xbu f
no. 6976- 4 /29 LC72151V parameter symbol pin ratings unit supply voltage v dd max v dd * C0.3 to +6.5 v av dd * C0.3 to +11.0 v in 1 max ce, cl, di C0.3 to +7.0 v in 2 max xin, fmin, amin, hctr/i-3, lctr/i-4, C0.3 to v dd + 0.3 maximum input voltage ain2, tgi1, tgi2, tgo v v in 3 max i/o-1, i/o-2 C0.3 to +15.0 v in 4 max ain1, aref C0.3 to +6.5 v o 1 max do C0.3 to +7.0 v o 2 max xout, pdm1, pdm2, pds, pdf, xbuf, tgi1, C0.3 to v dd + 0.3 maximum output voltage tgi2, tgo v v o 3 max i/o-1, i/o-2, o-3, aout2 C0.3 to +15.0 v o 4 max aout1 C0.3 to +11.0 i o 1 max i/o-1, i/o-2, o-3 0 to 10.0 maximum output current i o 2 max do, tgi1, tgi2, tgo, aout1, aout2 0 to 5.0 ma i o 3 max xbuf 0 to 3.0 allowable power dissipation pd max (ta 85 c) ssop30 :160 mw operating temperature topr C40 to +85 c storage temperature tstg C55 to +125 c specifications absolute maximum ratings at ta = 25 c, v ss = av ss = 0 v note: power must be applied to av dd before applying to v dd and av dd must be higher than or equal to v dd . capacitors of at least 0.1 f must be inserted between the v dd and v ss , and between the av dd and av ss power supply pins. parameter symbol pin conditions ratings unit min typ max v dd 1 v dd v dd av dd 4.5 5.5 supply voltage v dd 2 av dd v dd av dd 7.5 8.5 9.5 v v dd 3 v dd serial data retention voltage 2.0 v ih 1 ce, cl, di 0.7v dd 6.5 high-level input voltage v ih 2 i/o-1, i/o-2 0.7v dd 13 v v ih 3 hctr/i-3, 0.7v dd v dd lctr/i-4 ce, cl, di, low-level input voltage v il 1 i/o-1, i/o-2, 0 0.3v dd v lctr/i-4 v il 2 hctr/i-3 0 0.2v dd v o 1 do 0 6.5 output voltage v o 2 aout1 0 9.5 v v o 3 i/o-1, i/o-2, o-3, 0 13 aout2 f in 1 xin v in 1 * 1 7 11 f in 2 fmin v in 2 * 1 10 160 f in 3 amin (sns=1) v in 3 * 1 2 40 mhz input frequency f in 4 amin (sns=0) v in 4 * 1 0.5 10 f in 5 hctr/i-3 v in 5 * 1 0.4 25 f in 6 lctr/i-4 v in 6 * 1 10 500 khz f in 7 lctr/i-4 v in 7 * 2 1.0 20 10 3 hz allowable operating ranges at ta = C40 to 85 c, v ss = av ss = 0 v continued on next page.
no. 6976- 5 /29 LC72151V parameter symbol pin conditions ratings unit min typ max v in 1 xin f in 1 200 1500 v in 2-1 fmin f = 10 to 50 mhz 40 1500 v in 2-2 fmin f = 50 to 130 mhz 20 1500 v in 2-3 fmin f = 130 to 160 mhz 40 1500 v in 3 amin (sns=1) f in 3 40 1500 input amplitude v in 4 amin (sns=0) f in 4 40 1500 mvrms v in 5-1 hctr/i-3 f = 0.4 to 25 mhz * 3 40 1500 v in 5-2 hctr/i-3 f = 8 to 12 mhz * 4 70 1500 v in 6-1 lctr/i-4 f = 10 to 400 khz * 3 40 1500 v in 6-2 lctr/i-4 f = 400 to 500 khz * 3 20 1500 v in 6-3 lctr/i-4 f = 400 to 500 khz * 4 70 1500 guaranteed crystal oscillator xtal xin, xout * 5 10.25 10.35 mhz frequency ranges notes: 1. sine wave with capacitor coupled. 2. pulse wave with dc coupled. 3. serial data: ctc = 0 4. serial data: ctc = 1 5. recomended ci value for the crystal oscillator: ci 70 the circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and oth er items. therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability. continued from preceding page. parameter symbol pin conditions ratings unit min typ max rf1 xin 1 m rf2 fmin 500 internal feedback resistance rf3 amin 500 k rf4 hctr/i-3 500 rf5 lctr/i-4 500 internal pull-down resistance rpd1 fmin 50 100 300 k rpd2 amin 50 100 300 hysteresis v his ce, cl, di, lctr/i-4 0.1 v dd v v oh 1 pdm1, pdm2, pds, pdf i o = C 1 ma v dd C 1.0 high-level output voltage i o = C 2 ma v dd C 2.0 v v oh 2 aout1 i o = C 1 ma av dd C 1.0 v oh 3 xbuf i o = C 0.5 ma v dd C 1.5 v ol 1 pdm1, pdm2, pds, pdf i o = 1 ma 1.0 i o = 2 ma 2.0 v ol 2 aout1 i o = 1 ma 1.0 v ol 3 xbuf i o = 0.5 ma 1.5 low-level output voltage i o = 1 ma 0.2 v v ol 4 i/o-1, i/o-2, o-3 i o = 5 ma 1.0 i o = 8 ma 1.6 v ol 5 do i o =1 ma 0.2 i o = 5 ma 1.0 v ol 6 aout2 i o = 1 ma, ain2 = 1.3 v 0.5 i ih 1 ce, cl, di v i = 6.5 v 5.0 i ih 2 i/o-1, i/o-2 v i = 13 v 5.0 i ih 3 hctr/i-3, lctr/i-4 v i = v dd 5.0 a high-level input current i ih 4 xin v i = v dd 0.11 0.9 i ih 5 fmin, amin, hctr/i-3, v i = v dd 1.8 15 lctr/i-4 i ih 6 ain1, aref v i = 5.5 v 0.01 100 na i ih 7 tgi1, tgi2, tgo v i = v dd 3.0 a electrical characteristics in the allowable operating ranges continued on next page.
no. 6976- 6 /29 LC72151V parameter symbol pin conditions ratings unit min typ max i il 1 ce, cl, di v i = 0 v 5.0 i il 2 i/o-1, i/o-2 v i = 0 v 5.0 i il 3 hctr/i-3, lctr/i-4 v i = 0 v 5.0 a low-level input current i il 4 xin v i = 0 v 0.11 0.9 i il 5 fmin, amin, hctr/i-3, v i = 0 v 1.8 15 lctr/i-4 i il 6 ain1, aref v i = 0 v 0.01 100 na i il 7 tgi1, tgi2, tgo v i = 0 v 3.0 a v in = 8.5 v, i = 3 ma, 70 140 av dd = 8.5 v analog switch on resistance r on tgi1, tgi2, tgo v in = 4.5 v, i = 3 ma, 50 100 av dd = 8.5 v v in = 0.5 v, i = 3 ma, 70 140 av dd = 8.5 v i off 1 aout1 v o = 6.5 v 5.0 output off leakage current i off 2 i/o-1, i/o-2, o-3, aout2 v o = 13 v 5.0 a i off 3 do v o = 6.5 v 5.0 high-level 3-state off leakage current i offh pdm1, pdm2, pds, pdf v o = v dd 0.01 200 na low-level 3-state off leakage current i offl pdm1, pdm2, pds, pdf v o = 0 v 0.01 200 na input capacitance c in fmin 6 pf xtal = 10.35 mhz i dd 1 v dd f in 2 = 160 mhz 10 18 v in 2 = 40 mvrms pll block stopped i dd 2 v dd (pll inhibit) 0.5 1.5 xtal osc operating ma supply current (xtal = 10.35 mhz) pll block stopped i dd 3 av dd (pll inhibit) 1.5 xtal osc stopped on-chip op-amp stopped pll block stopped i dd 4 v dd (pll inhibit) 10 a xtal osc stopped on-chip op-amp stopped continued from preceding page.
no. 6976- 7 /29 LC72151V pin functions pin no. symbol usage function pin circuit ? crystal oscillator connection. (10.25 or 10.35 mhz) 30 1 xin xout xtal osc ? fmin is selected by setting dvs in the control data to 1. ? enters high-speed locking mode by setting sns in the control data to 1. ? enters normal mode by setting sns in the control data to 0. ? input frequency: 10 to 160 mhz ? the signal is transmitted to the swallow counter. ? the divisor can be set to a value in the range 272 to 65,535. 8 fmin local oscillator signal input ? amin is selected by setting dvs in the control data to 0. ? when sns in the control data is set to 1: input frequency: 2 to 40 mhz the signal is directly transmitted to the swallow counter. ? when sns in the control data is set to 0: input frequency: 0.5 to 10 mhz the signal is directly transmitted to the 12-bit programmable divider. the divisor can be set to a value in the range 5 to 4,095. 9 amin local oscillator signal input ? this pin must be set to the high level when inputting serial data to the LC72151V di pin and when outputting serial data from the do pin. 29 ce chip enable s ? serial data input for transferring data from the controller to the LC72151V. 28 di input data s ? data synchronization clock signal used when inputting serial data to the LC72151V di pin and when outputting serial data from the do pin. 27 cl clock s ? serial data output for transferring data from the LC72151V to the controller. 26 do output data ? LC72151V power supply. a voltage in the range 4.5 to 5.5 v must be provided when the pll circuit is operating. ? the power-on reset circuit operates when power is first applied. note: power must be applied to av dd before applied to v dd and av dd must be higher than or equal to v dd . 6 v dd power ? LC72151V ground. 7 v ss ground ? input/output dual function pins ? the function will be selected according to ioc1 and ioc2 in the control data. data = 0: input port 1: output port ? when specified as an input port: the input pin state is transmitted to the system microcontroller from do pin. input state = low: data is 0 = high: data is 1. ? when specified as an output port: the output state will be determined according to i/o-1 and i/o-2 in the control data. data = 0: low = 1: open ? these pin function as an input port at a power-on reset. 2 3 i/o-1 i/o-2 i/o ports continued on next page.
no. 6976- 8 /29 LC72151V continued from preceding page. pin no. symbol usage function pin circuit ? dedicated output pin ? latches out3 in the control data and outputs data from o-3 pin. ? this pin goes open state at a power-on reset. 5 o-3 output port ? op-amp for pll active low-pass filter ? av ss is the analog system ground pin shared with low-pass filter nch mos transistor. ? voltage applied to aref pin must be 1/2 that to v dd pin. note: power must be applied to av dd before applied to v dd , and av dd must be higher than or equal to v dd . 19 12 13 14 15 ain1 aref av dd av ss aout1 op-amp for low-pass filter amp ar ef ain 1 + ao u t 1 av ss av dd ? pll active low-pass filter nch mos transistor ? source of the transistor is connected to av ss pin. note: connect av ss pin to ground in use. 24 25 ain2 aout2 transistor for low-pass filter amp av ss ? pll charge pump output when the frequency created by dividing the local oscillator signal frequency by n is higher than the reference frequency, a high level is output from the pd pin. when lower, a low level is output. the pd pin goes to the high-impedance state when the frequencies match. 21 23 20 pdm1 pdm2 pds charge pump output ? pll high-speed locking charge pump output when the high-speed locking mode is selected, signal pulses is output according to the frequency variation. this pin enters high- impedance state when the local oscillation frequency enters the set frequency range. 22 pdf pll high-speed locking charge pump output ? pll high-speed locking active low-pass filter transmission gate input/output dual function pins note: connect av ss pin to ground in use. 18 17 16 tgi1 tgi2 tgo pll high-speed locking tg tgo tgi2 tgi1 ? hctr is selected by setting cts1 in the control data to 1. input frequency: 0.4 to 25 mhz the signal is input to a divide-by-2 circuit and the result is input to a general-purpose counter. this counter can also be used as an integrating counter. the counter value is output as the result of the count, msb first, from the do pin. there are four measurement periods: 4, 8, 32, and 64 ms. ? when h/i-3 in the control data is set, this pin functions as an input port, and the value is output from the output pin do. 10 hctr/i-3 general-purpose counter ? lctr is selected by setting cts1 in the control data to 1. ? when the lctr is selected as described above and cts0 is set to 1: this pin enters the frequency measurement mode. input frequency: 10 to 500 khz the signal is directly transmitted to the general-purpose counter. ? when cts0 is set to 0 this pin enters period measurement mode. input frequency: 1 hz to 20 khz period can be measured either in single period or in double period. if double period measurement is selected, the frequency is 2 hz to 40 khz. the counter value is output as the result of the count, msb first, from the do pin. ? when l/i-4 in the control data is set: this pin functions as an input port, the value is output from the output pin do. 11 lctr/i-4 general-purpose counter continued on next page.
serial data i/o methods data is input to and output from the LC72151V using the sanyo ccb (computer control bus) format, which is the serial bus format used by sanyo audio ics. this ic adopts a ccb format with an 8-bit address. no. 6976- 9 /29 LC72151V i/o mode address content b0 b1 b2 b3 a0 a1 a2 a3 ? control data input (serial input) mode. [1] in1 (82) 0 0 0 1 0 1 0 0 ? 32 bits of data are input. ? see the di control data (serial data input) structure item for details on the content of the input data. ? control data input (serial input) mode. [2] in2 (92) 1 0 0 1 0 1 0 0 ? 32 bits of data are input. ? see the di control data (serial data input) structure item for details on the content of the input data. ? data output (serial data output) mode. [3] out (a2) 0 1 0 1 0 1 0 0 ? the number of bits output is equal to the number of clock cycles. ? see the do output data (serial data output) structure item for details on the content of the output data. fir i/o mode determined s t d ata i n 1 /2 fir s t d ata o u t fir s t d ata o u t a3 a2 a1 a0 b3 b2 b1 b0 di ce 1 cl cl : normally hi cl : normally low do 2 1 1 2 2 continued from preceding page. pin no. symbol usage function pin circuit ? output buffer for the crystal oscillator circuit ? when xb in the serial data is set to 1, the output buffer operates and the crystal oscillator signal (a pulse signal) is output. when xb is 0, xbuf outputs a low level. after the power-on reset, the output buffer is fixed at the low level. 4 xbuf crystal oscillator buffer xout
di control data (serial data input) structure (1) in1 mode no. 6976- 10 /29 LC72151V r2 r1 r0 p dc1 p dc0 dv s sn s p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 (16) res e t (5) u -ct r (4) d o-c (3) r -ct r (2) p d-c (1) p -ct r p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 r3 0 0 1 0 1 0 0 di address address * : don? care 0 gt0 ct s 1 ct s 0 ct e rs t dt 1 dt 0 gt1 ul1 ul0 uld il 1 il 0 l /i- 4 h /i- 3 hs e 1 hs e 0 cws 1 cws 0 tlr 1 tlr 0 xs xb out3 out2 out1 i/o * * * - 2 i/o - 1 0 0 1 0 1 0 0 di 1 tes t 2 tes t 1 tes t 0 dz 1 dz 0 dlc tes t 3 ( 1 8 ) xtal (17) don' t c are (15) te s t (11) dz-c (10) p d -l (9) u nl oc k (4) d o-c ( 8 ) u /i- c (5) u -ct r (14) hs tm r (13) cws - d (12) tlr-d (7) o -p or t (6) i / o -c ct c ct p (17) don' t c are (2) in2 mode
no. 6976- 11 /29 LC72151V di control data description no. control block/data content related data ? this data sets the divisor for the programmable divider and p15 is the msb of this binary value. lsb will change according to the dvs and sns. * : when the lsb is p4, p0 to p3 are invalid. ? used to select programmable divider signal input pins (fmin, amin) and to switch the input frequency range. * : when the dvs and sns are set to 1, the high-speed locking mode is selected, the high- speed control data becomes valid. by setting dvs to 1 and sns to 0 this pin enters fmin mode, the sub-charge pump control data is valid, the high-speed locking control data becomes invalid. (1) programmable divider data p0 to p15 dvs, sns ? this data controls the sub-charge pump. ( * : dont care) ? the sub-charge pump can be used in conjunction with the pdm1 or the pdm2 pin (main charge pump pin) to form a high-speed locking circuit. * : fmin(high-speed mode): setting dvs and sns to 1 forces the sub-charge pump to operate for the time set due to the high-speed locking end flag output wait time, and allows the locking time to be reduced after switching to the normal pll mode. see the charge pump structure item for details. hse0 hse1 (2) sub-charge pump control data pdc0, pdc1 ? reference frequency selection data note: pll inhibit (backup mode) the programmable divider block is stopped, the fmin and amin pins are pulled down to ground, and the charge pump output is set to the floating state. (3) reference divider data r0 to r3 pdc1 pdc0 sub-charge pump state 0 * high impedance 1 1 charge pump operating (at all times) 1 0 charge pump operating (when pll unlocked) dvs sns lsb set divisor (n) 1 1 p0 272 to 65535 1 0 p0 272 to 65535 0 1 p0 272 to 65535 0 0 p4 4 to 4095 dvs sns input pin input pin frequency range 1 1 fmin 10 to 160 mhz (high-speed mode) 1 0 fmin 10 to 160 mhz (normal mode) 0 1 amin 2 to 40 mhz 0 0 amin 0.5 to 10 mhz r3 r2 r1 r0 reference frequency (khz) 0 0 0 0 50 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 3.125 1 0 0 0 10 1 0 0 1 9 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 1 1 0 1 30 1 1 1 0 pll inhibit + xtal osc stop 1 1 1 1 pll inhibit continued on next page.
no. 6976- 12 /29 LC72151V continued from preceding page. no. control block/data content related data ? data that determines the output of the do pin * note: open state will be selected at the power-on reset. note: * 1. end-uc: general-purpose counter operation completion check however, if i/o-1 and i/o-2 are set to output mode, they change from in to the open state. * : do pin state during data input (in1, in2 modes, ce = high) keeps open regardless of the do pin control data. in addition, do pin during data input (out mode, ce = high) outputs the value for the internal do serial data synchronized with the cl regardless of the do pin control data. caution: cannot be used in crystal oscillator stop mode: r0 = 0, r1 = r2 = r3 = 1 (the do pin will not change state.) (1) when the count operation starts by setting end-uc with cte set to 1 from 0, do pin automatically goes to open state. (2) when the general-purpose counter operation ends, the do pin goes low, it is allowed to check the count end. (3) do pin goes to open state according to the serial data input/output state: ce pin = high. (4) do pin control data uld dt0, dt1 il0, il1 cte i/o-1 i/o-2 uld dt1 dt0 do pin 0 0 0 low when unlocked 0 0 1 open 0 1 0 end-uc * 1 0 1 1 in * 2 1 0 0 open 1 0 1 open 1 1 0 end-uc * 1 1 1 1 in * 2 il1 il0 in 0 0 open 0 1 i-1 (pin state) 1 0 i-2 (pin state) 1 1 do goes low when i-1 changes. do (1) start (2) completion (3) ce: hi continued on next page. note: * 2.
no. 6976- 13 /29 LC72151V no. control block/data content related data ? selects the general-purpose counter input pins (hctr, lctr). ? general-purpose counter measurement start data cte = 1: starts the counter. cte = 0: resets the counter. ? determines the measurement time (frequency mode) and number of periods (period mode). ? when cte = 0, input pull-down is disabied by setting ctp to 1 note: wait time: 1 to 2ms. however, ctp must be set to 1 4ms before cte is set to 1. ? the input sensitivity is reduced when ctc is set to 1. (sensitivity: 10 to 30 mv rms) * : refer to the general-purpose counter stracture on page 22 for details. (5) general-purpose counter control data cts0, cts1 cte gt0, gt1 ctp ctc ? data that specifies the i/o direction of the i/o ports (i/o-1, i/o-2). [data] = 0: input port 1: output port * : after the power-on reset, the i/o-1 and i/o-2 are set up as input ports. out1, out2 (6) i/o port control data io-1, i/o-2 ? data that determines the output from output ports o-1 to o-3. [data] = 0: open 1: low * : invalid when the corresponding port is set up as an input port. * : at a power-on reset, open state is selected by selling the data to 0 i/o-1, i/o-2 (7) output port data out1 to out3 ? data that switch the function between general-purpose counter and input port. h/i-3 = 0: i-3 (input port) 1: hctr (gereal-purpose counter) l/i-4 = 0: i-4 (input port) 1: lctr (gereal-purpose counter) cts0, cts1 (8) general-purpose counter control data h/i-3, l/i-4 continued from preceding page. frequency measurement period measurement gt1 gt0 measurement time wait time mode ctp = 0 ctp = 1 0 0 4 ms 3 to 4 ms 1 to 2 ms one period 0 1 8 3 to 4 ms 1 to 2 ms one period 1 0 32 7 to 8 ms 1 to 2 ms two periods 1 1 64 7 to 8 ms 1 to 2 ms two periods continued on next page. cts1 cts0 input pin measurement mode 1 * hctr frequency 0 1 lctr frequency 0 0 lctr period
no. 6976- 14 /29 LC72151V continued from preceding page. no. control block/data content related data ? width selection for the phase error (?e) detection function used to determine the pll locked/unlocked state. when a phase error greater than the ?e detection width from the table occurs, the pll circuit is seen as in the unlocked state. * : when unlocked, the do pin goes low and the serial data output is ul = 0. uld dt0, dt1 dvs sns (9) unlock state detection data ul0, ul1 ? controls the phase comparator dead band. * : the phase comparator operates in dza mode after the power-on reset. (recomended modes: dzd, dzc) (11) phase comparator control data dz0, dz1 ? bit that forcible sets the charge pump output to the low level. dlc = 1: low level dlc = 0: normal operation * : if a deadlock occurs due to the vco control voltage (vtune) going to zero and stopping the vco oscillator, set the charge pump output to the low level and set vtune to v cc to escape from the deadlocked state (deadlock clearing circuit). normal operation is selected after the power-on reset. (10) charge pump control data dlc ? data to control the frequency in the convergence range to judge the high-speed locking control completion. this data is valid when fmin (high-speed mode) is selected by setting dvs and sns to 1. * : the convergence range is 200 khz at a power-on reset. refer to description of the high-speed locking control system (p.19) for details. (12) high-speed locking convergence range control data tlr0, tlr1 ul1 ul0 ?e detection width detection output xtal 0 0 stopped open 10.25 m/10.35 mhz 0 1 0 directly outputs ?e 10.25 m/10.35 mhz 0.49 s ?e is extended by 10.25 mhz 0.1 to 0.2 ms. 1 0 0.49 s ?e is extended by 10.35 mhz 0.11 to 0.22 ms. (fr = 30/9/3 k) 0.43 s ?e is extended by 10.35 mhz (other 0.1 to 0.2 ms. than fr = 30/9/3 k) 0.98 s ?e is extended by 10.25 mhz 0.1 to 0.2 ms. 1 1 0.97 s ?e is extended by 10.35 mhz 0.11 to 0.22 ms. (fr = 30/9/3 k) 0.87 s ?e is extended by 10.35 mhz (other 0.1 to 0.2 ms. than fr = 30/9/3 k) 0.1 to 0.22ms e do extended unlock state output dz1 dz0 dead band mode 0 0 dza 0 1 dzb 1 0 dzc 1 1 dzd tlr1 tlr0 convergence range [khz] 0 0 50 0 1 100 1 0 150 1 1 200 continued on next page.
no. 6976- 15 /29 LC72151V continued from preceding page. no. control block/data content related data ? data to control the wait time in the high-speed locking. this data is valid when the fmin (high-speed mode) is selected by setting dvs and sns to 1. * : the wait time is 20 s at a power on reset. refer to description of the high-speed locking control system (p.19) for details. dvs sns (13) high-speed locking charge wait time control data cws0, cws1 ? crystal oscillator selection data xs = 0: 10.25 mhz = 1: 10.35 mhz ? crystal oscillator buffer (xbuf) xb = 0: buffer output is turned off. xb = 1: buffer output is turned on. * : xb = 0: buffer output is turned off at a power-on reset. r0 to r3 (18) crystal oscillator circuit xs xb ? ic test control data these bits must be set as follows during normal operation. test0 = 0 test1 = 0 test2 = 0 test3 = 0 * : after the power-on reset, the test data is all set to zero.? (15) ic test data test0 test1 test2 test3 cws1 cws0 wait time [ s] 0 0 2.5 0 1 5 1 0 10 1 1 20 ? data to control the wait time after the high-speed locking control completes till the operation is switched to the normal pll operation. this data is valid when the fmin (high-speed mode) is selected by setting dvs and sns to 1. during the wait time, the unlock signal is forcibly output, the sub-charge pump allows to be operated. thereby, reduces the locking time after switching to the normal pll operation. * : the wait time is 400 s at a power on reset. refer to description of the high-speed locking control system (p.19) for details. dvs sns pdc0 pdc1 (14) high-speed locking completion flag output wait time control data hse0, hse1 hse1 hse0 wait time [ s] 0 0 0 0 1 200 1 0 400 1 1 800 (16) reset rst ? this data resets the LC72151V. * : after the power is first applied, the power-on reset circuit initializes the ic. however, the data must be set to 1 to ensure the initialization. (17) dnc ? set data to 0 ?note: after power is first applied, the power-on reset circuit initializes the ic. however, the ccb data (rst) must be input to the i c to ensure the initialization.
structure of the do output data (serial output data) (3) out mode no. 6976- 16 /29 LC72151V c1 c2 c3 (2) unloc k (1) in - port c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 (3) if-ctr c14 c15 c16 c17 c18 c19 ul c0 0 * * * * 0 1 0 address 1 0 1 do * : bits that are set to 0. di 0 i1 * * * i2 i3 i4 no. control block/data content related data ? the bits i1 to i4 are set to the latched states of the i/o pins i/o-1 and i/o-2 and the input pins hctr/i-3 and lctr/i-4. these states are latched at the point the ic enters data output mode. the pin states are latched regardless of the pin mode (input or output). i1, i2 ? i/o-1 and i/o-2 pin states i3, i4 ? hctr/i-3 and lctr/i-4 pin states i/o-1 i/o-2 h/i-3 l/i-4 (1) i/o port data i4 to i1 ? data created by latching the value for the unlock detection circuit ul ? 0: unlocked 1: locked or in detection halt mode ul0 ul1 (2) pll unlock data ul ? data created by latching the value for the if counter (20-bit binary counter) c19 ? msb of the binary counter c0 ? lsb of the binary counter cte gt0 gt1 (3) if counter binary counter c19 to c0 pin state = high: 1 low: 0
serial data input (in1/in2) t su , t hd , t el , t es , t eh , > 0.45 s t lc < 0.45 s no. 6976- 17 /29 LC72151V t lc t eh t es t el t hd t su r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di internal data internal data ce cl t lc t eh t es t el t hd t su r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di ce cl do t dc t dc t dh t eh t es t el t hd t su i1 i3 i2 i4 a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 c2 c3 di ce cl do t dc t dc t dh t eh t es t el t hd t su i2 i3 i4 i1 a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 c2 c3 di ce cl serial data output (out) t su , t hd , t el , t es , t eh > 0.45 s t dc , t dh < 0.2 s note: the do pin is an n-channel open drain output, and thus the data switching time will differ depending on the value of the pull-u p resistor used and the printed circuit board capacitance. (1) cl: normally high (2) cl: normally low (1) cl: normally high (2) cl: normally low
no. 6976- 18 /29 LC72151V serial data timing t cl t eh t es t hd t su t lc t dh t dc t dc t el t ch v il v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch operation old new internal data latch operation old new cl di ce t ch t eh t es t hd t su t lc t dh t dc t el t cl v il v il v ih v ih v ih v ih v ih v ih v il v il v il do cl di ce parameter symbol pin conditions ratings unit min typ max data setup time t su di, cl 0.45 s data hold time t hd di, cl 0.45 s clock low-level period t cl cl 0.45 s clock high-level period t ch cl 0.45 s ce wait time t el ce, cl 0.45 s ce setup time t es ce, cl 0.45 s ce hold time t eh ce, cl 0.45 s data latch change time t lc 0.45 s data output time t dc do, cl depends on the value of the pull-up 0.2 s t dh do, ce resistor used. allowable operating ranges at ta = C40 to 85 c, v ss = 0 v note: see the timing chart for serial data transfers.
description of the high-speed locking control system the LC72151V realizes the maximum inter-band edge high-speed locking time 500 s by optimizing the filter constants and internal status setting when the fmin (high-speed mode) by setting dvs and sns to 1. the following describes the high-speed locking control system. procedure the LC72151V operates as shown below when selecting fmin (high-speed mode) and setting sub-charge pump operation during unlocked. control data setting data (ccb) necessary for the new high-speed locking control is described below. this data is valid when the fmin (high-speed mode) is selected by setting dvs and sns to 1. * : the recommended values are for reference purpose only, not the guarantee values for the fastest locking time. no. 6976- 19 /29 LC72151V change value n pdf/pdm1/pdm2/pds/tgi1/tgi2 pin states pdf pdm1 * : : operating; : stopped (high-impedance) pdm2 pds tgi1 tgi2 ? ? ? new high-speed locking control (when the value n variation is under 16, only operates the normal pll.) stops the sub-charge pump and only the main-charge pump operates. (normal locking state) operates normal pll when the local oscillation frequency enters the high-speed locking frequency range. (the sub-charge pump operates for the time set by the high-speed locking completion flag output wait time.) ccb data name (selectable set value) description recommended value the new high-speed locking control controls the convergence of the target frequency into the set frequency range. this data can be used to set the frequency range for convergence judgement. * : as the convergence range narrower, the locking time tends to be shorter. tlr0 = 0 tlr1 = 0 ( 50 khz) tlr0/tlr1 high-speed locking convergence range ( 50/100/150/200 khz) during the new high-speed locking control, charge application from the pdf pin and local oscillation frequency measurement for the fmin pin are repeatedly implemented. this data can be used to set the vt voltage stable time after the charge is applied until the local oscillator frequency is measured. * : voltage stable time vt changes according to the peripheral circuit. cws0 = 1 cws1 = 0 (5 s) cws0/cws1 high-speed locking charge wait time (0/2.5/5/10 s) after the new high-speed locking control ends, since the phase remains in convergence state in the internal unlock detection circuit until the locking judgement is implemented, the sub-charge pump will not operate by the sub-charge pump operation setting during unlocked. this data can be used to set the time to force the sub-charge pump to operate for after the new high-speed locking control completes. * : after the new high-speed locking control completes, the locking time tends to be shortened by operating the sub-charge pump for an adequate time. hse0 = 0 hse1 = 1 (400 s) hse0/hse1 high-speed locking completion flag output wait time (0/100/200/400 s)
block diagram no. 6976- 20 /29 LC72151V pd m 1 pd m 2 p has e det e c t or unl o c k det e c t or and s ubc harge pu m p c o n t unl o c k pd s pd f fas t lock u p cont rol ref e renc e d i v i der p r ogram m abl e d i v i der register register register frequenc y c ount er xi n fm in ccb ( c e,d i,c l ) gat e ti me s y s t e m cl o c k f or f a st lo ck up co nt rol tgi1 tgi2 tgo + av ss ar ef ain 1 av dd ao u t vco
charge pump structure note: if the unlock state is detected when the channel changes, the sub-charge pump (pds) operates. since the sub- charge pump operates concurrently with the main-charge pump, decrease the time constants for the low-pass filter to accelerate the locking. however, note that when the fmin (high-speed mode) is selected and when the channel changes (during high- speed locking control), both the main- and the sub-charge pumps do not operate and enter the high impedance state, and forcibly implement an unlock judgement. when locked at a high-speed locking control completion, the output is not extended but locking is instantaneously judged. by selecting sub-charge operation (during unlocked) with fmin (high-speed mode) selected, the sub-charge pump is forcibly operated to shorten the locking time for the time set by the high-speed locking completion flag output wait time control data (hse0, hse1) after switching from high-speed locking control to normal pll operation. no. 6976- 21 /29 LC72151V pd m 1 (m a i n) (m a i n) pd m 2 fv co /n p has e det e c t or unl o c k det e c t or and s ubc harge pu m p c o n t fr e f cl oc k unl o c k dz 0 ul0 ul1 p dc0 p dc1 do dlc dz 1 (s ub ) pd s pd new high-speed locking charge pump main-charge pump main-charge pump conventional high-speed locking sub-charge pump f (hi g h s peed) fas t lock u p cont rol tlr 0 ,tlr 1 cw s 0 , c w s 1 h se0 ,h se1 pdc1 pdc0 pds(sub-charge pump state) 0 * high impedance 1 1 charge pump operating (at all times) 1 0 charge pump operating (when pll unlocked) dlc pdm1, pdm2, pds 0 normal operation 1 forced low
general-purpose counter structure no. 6976- 22 /29 LC72151V 4? 8?1 12?5 16?9 0? s1 s2 s3 ct s 0 ct s 1 (t ) (f i f ) gt gt1, gt0 m s b l s b ct c = fif gt c = (1/t) ? 900khz e hct r single period/ double period extraction circuit lctr 1 2 4/ 8/ 32/ 64 ms do pin general-purpose counter (20-bit binary counter) i/o signal switching gate check signal parameter lctr period measurement mode check signal frequency xtal osc 10.25 mhz 10.35 mhz fref = 30, 9, 3 khz fref = other than 30, 9, 3 khz check signal 1025 khz 1030 khz 1150 khz cts1 cts0 input pin measurement mode frequency range input sensitivity s1 1 * hctr frequency 0.4 to 25.0 mhz 40 mvrms * 1 s2 0 1 lctr frequency 10 to 500 khz 40 mvrms * 1 s3 0 0 lctr period 1.0 to 20 10 3 hz (pulse) * 1: ctc = 0: 40 mvrms ctc = 1: 70 mvrms : no stipulation ( not guaranteed) ( ): actual value (reference value) hctr: minimum input sensitivity regulation f [mhz] ctc 0.4 f < 8 8 f < 12 12 f 25 0 (normal mode) 40 mvrms 40 mvrms 40 mvrms (5 to 15 mvrms) 1 (degrade mode) 70 mvrms (40 to 60 mvrms) lctr: minimum input sensitivity regulation f [mhz] ctc 10 f< 400 400 f 500 0 (normal mode) 40 mvrms 20 mvrms (1 to 10 mvrms) 1 (degrade mode) 70 mvrms (15 to 30 mvrms) gt1 gt0 frequency measurement mode period measurement mode measurement time wait time 0 0 4 ms 3 to 4 ms 1 period 0 1 8 1 0 32 7 to 8 ms 2 periods 1 1 64 ctc: input sensitivity select data. input sensitivity is degraded by setting ctc to 1. however, the actual value for hctr is in the range 40 to 60 mvrms at 10.7 mhz, for lctr is in the range 15 to 30 mvrms at 450 khz. ctp: input pull-down can be inhibited by setting ctp to 1. set ctp to 1 4 ms before setting cte to 1. set ctp to 0 when the counter is not used. wait time will be reduced to 1 to 2 ms by setting ctp to 1.
the LC72151Vs general-purpose counter is a 20-bit binary counter. the result of the count operation can be read out msb first from the do pin. the measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or 64 ms by the gt0 and gt1 bits. the frequency of the input to the hctr pin can be measured by determining how many pulses were input to the general-purpose counter during this measurement time. when the general-purpose counter is used to measure the frequency, the period of the signal input to lctr pin can be measured by counting the number of check signals input to the general-purpose counter for the one or two periods of the signal input to the lctr pin. reset the general-purpose counter in advance by setting cte to 0 before starting the counter. a general-purpose counter count operation is started by setting the cte bit in the serial data to 1. the serial data takes effect internally to the LC72151V when the ce pin input level is changed from high to low. the input to the hctr pin must be provided before the wait time has elapsed after ce was set low. next, the result of the general-purpose counter count after the measurement completes must be read out while cte is still set to 1. this is because the general-purpose counter is reset when cte is set to 1. never fail to reset the general-purpose counter before starting the count operation of the general-purpose counter. in addition, the signal input to lctr pin is directly transmitted to the general-purpose counter. note that the signal input to the hctr pin is first divided by 2 internally to the ic and then input to the general-purpose counter. therefore, the result of the general-purpose counter count is a value that corresponds to 1/2 of the frequency actually input to the hctr pin. no. 6976- 23 /29 LC72151V ct measurement time e = 1 ce gt end-uc t : wait time wu t wu start completion internal data latch (cte) general- purpose counter ct e = 0 res e t sta r t res integrates end of the count operation end of the count operation t art ct e = 1 ct e = 1 ce gt end-uc (do) when used as an integrating counter in integrating count mode, the count value of the general-purpose counter is accumulated. care must be taken to handle counter overflow correctly. the count value will be in the range 0 h to fffff h . ?resets the general-purpose counter ?starts the general-purpose counter ?restarts the counter if set to 1 again. 1 ? * cte: 0 ?
other items (1) notes on the phase detector dead band when the charge pump operates in on/on mode, the charge pump generates correction pulses even when the pll is locked. here, it is easy for the loop to become unstable, and special care is required in designs that use this mode. the following problems may occur in on/on mode. ? side bands may be generated due to reference frequency leakage. ? side bands may be generated due low-frequency leakage due to the envelope of the correction pulses. no. 6976- 24 /29 LC72151V dz1 dz0 dead band mode charge pump dead band 0 0 dza on/on C C0 s 0 1 dzb on/on C0 s 1 0 dzc off/off +0 s 1 1 dzd off/off ++0 s when a dead band is present (off/off mode), the loop will be stable, but it will be harder to acquire a good c/n ratio. on the other hand, with the mode that does not have a dead band (on/on mode), it will be easier to acquire a high c/n ratio, but harder to acquire loop stability. therefore, the dza and dzb modes, in which there is no dead band, can be effective if either a high signal-to-noise ratio of 90 to 100 db in fm reception or an increased pilot margin in am stereo reception is required. inversely, if such a high fm signal-to-noise ratio is not required for fm reception, or an adequate pilot margin can be acquired for am stereo reception, then the dzc and dzd modes, in which a dead band is present, may be more effective. dead zone (dead band) definition the phase comparator compares fp with the reference frequency (fr) as shown in figure 1. this circuit outputs a voltage v (a) that is proportional to the phase difference ? as shown in figure 2. however, due to internal delays and other factors, the actual ic is unable to compare small phase differences, and thus a dead zone (b) appears in the output. to achieve a high signal-to-noise ratio in the end product, the dead zone should be as small as possible. however, in popularly-priced models, there are cases where a somewhat wider dead zone may be easier to work with. this is because in some situations, such as when a powerful signal is applied to the rf input, in popularly-priced models there may be rf leakage from the mixer to the vcc. when the dead zone is narrow, outputs to correct this leakage are output, that output in turn modulates the vco, and generates a beat signal with the rf. reference divider programmable divider vco lpf phase detector mix rf leakage fr fp ?(nsec) (b) (a) v dead zone figure 1 figure 2 (2) notes on the fmin, amin, hctr/i-3, and lctr/i-4 pins the coupling capacitor must be located as close as possible to these pins. a capacitance of approximately 100 pf is desirable. in particular, if the hctr/i-3 and lctr/i-4 pin capacitor is over about 1000 pf, the time required to reach the bias level may become excessive, and incorrect counting may occur due to the relationship with the wait time.
(3) notes on the if counting using hctr/i-3 and lctr/i-4 pins when counting the if frequency, the application microcontroller must test the state of the if ic sd (station detect) signal, and only if the sd signal is present, turn on the if counter buffer output and perform an if count operation. methods in which auto-search operations are implemented only using the if count may incorrectly stop at frequencies where no station is present due to leakage from the if counter buffer. (4) using the do pin at times other than data output mode, the do pin can also be used to check for general-purpose counter count operation completion, to output the unlock state detection signal, and to check for changes in the input pins. note that the states of the input pins (i/o-1 and i/o-2) can be directly input to the system microcontroller through the do pin. (5) power supply pins capacitors of at least 0.1 f must be inserted between the v dd and v ss power supply pins and between av dd and av ss to reduce noise. these capacitors must be located as close to the v dd and v ss , av dd and av ss pins as possible. additionally, power must be applied to av dd before applying to v dd , and av dd must be higher than or equal to v dd . (6) note on power application after power is first applied, the power-on reset circuit initializes the ic. however, the ccb data rst must be set to 1 to ensure the initialization. (7) notes on vco design the vco must be designed so that the vco oscillation does not stop if the control voltage (vtune) becomes 0 v. if it is possible for this oscillator to stop, use the charge pump control data (dlc) to forcible set vtune to vcc temporarily to prevent the pll circuit from deadlocking. (this function is called a deadlock clear circuit.) pin states during a power-on reset no. 6976- 25 /29 LC72151V lc72 151 v xo state power-on state f i-1 f o i-2 o: open l: low f: floating state power-on state u t i/o - 1 i/o - 2 xb u f o-3 v dd v ss fm in am in hct r/ i - 3 l c tr /i- 4 ar ef av dd av ss ao u t 1 x in ce di cl do ao u t 2 ain 2 pd m 2 pd f pd m 1 pd s ain 1 tgi1 tgi2 tgo
no. 6976- 26 /29 LC72151V sample application circuit xi n do xo u t i/o - 1 i/o - 2 s 1 30 2 3 4 5 6 7 8 9 10 11 12 29 28 27 26 25 24 23 22 21 20 xb u f o-3 v dd v ss am in fm in av dd av ss ao u t 1 cl ao u t 2 pd m 2 pd f pd m 1 ain 2 pd s tgi1 tgo tgi2 ain 1 13 14 15 19 18 17 16 l c tr /i- 4 hct r/ i - 3 di ce ar ef s s am vc o fm vc o sd tuner -s ystem s t -indi c a te f m /a m- if if -r e q ues t fm / a m -com ce di cl un l o ck sd end-u c u - c ount st - i n d i c do 2nd m i x e r v cc =8v v cc =8v v cc =8v 10. 25m / 10. 35m hz 200 8. 2k 100 4700pf 2k 0. 033 f 10k 22k 100pf 100pf 100pf 330 33pf 100 1000pf 4. 3k 5. 6k 0. 068 f 0. 01 f 3. 3k 3. 9k av ss * : the constants shown are for reference purpose only, but do not guarantee the operation. notes: 1. power must be applied to av dd before applying to v dd , and av dd must be higher than or equal to v dd . 2. aref is an op-amp reference input voltage pin and must be applied a voltage 1/2 v dd . the applied voltage requires to be applied from another power supply from v dd to prevent affections due to logic system noise or other factors.
LC72151V state setting examples 1. in the case of fmrf 87.5 mhz reception (xtal = 10.35 mhz/if = +10.8 mhz) fm vco = 98.3 mhz xtal = 10.35 mhz, fref = 50 khz : xs = 1, r0 = r1 = r2 = r3 = 0 fmin (high-speed mode) selected : dvs = 1, sns = 1 dead-zone mode = dzd : dz0 = dz1 = 1 programmable divider divisor 98.3 mhz ? 50 khz = 1966 ? 07ae (hex) high-speed locking control conditions high-speed locking convergence range = 50 khz : tlr0 = tlr1 = 0 high-speed locking charge wait time = 5 s : cws0 = 1, cws1 = 0 high-speed locking completion flag output wait time = 400 s : hse0 = 0, hse1 = 1 unlock detection width = 0.43 s : ul0 = 0, ul1 = 1 no. 6976- 27 /29 LC72151V p0 lsb first d a t a i n1 transmitted data transmitted data 1 0 1 1 di 8 0 00 00 0 10 1 101111000001101000000000000 2 p1 p2 p3 p4 p5 p6 p7 p8 p9 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 sn s dv s p dc0 p dc1 r0 r1 r2 r3 dt 0 dt 1 rs t ct e ct s 0 ct s 1 gt0 gt1 ea 7 0 b 0 0 0 ms b i/o - 1 lsb first d a t a i n2 1 1 di address address 9 1 00 00 0 0 * * * * * * 0 0100010010000000010110000 2 i/o * * * - 2 out1 out2 out3 xb xs tlr 0 tlr 1 cws 0 cws 1 hs e 0 hs e 1 h /i- 3 l /i- 4 ct p ct c il 0 il 1 uld ul0 ul1 dlc dz 0 dz 1 tes t 0 tes t 1 tes t 2 tes t 3 01 9 0 0 d 0 ms b [in1] [in2]
no. 6976- 28 /29 LC72151V 2. in the case of amrf 530 khz reception (xtal = 10.35 mhz/if = 10.8 mhz) am vco = 11.330 mhz xtal = 10.35 mhz, fref = 10 khz : xs = 1, r0 = r1 = r2 = 0, r3 = 1 xtal buffer on : xb = 1 amin selected : dvs = 0, sns = 1 dead-zone mode = dzd : dz0 = dz1 = 1 programmable divider divisor 11.330 mhz ? 10 khz = 1133 ? 046d (hex) p0 lsb first d a t a i n1 0 1 1 1 di 8 0 00 00 0 10 1 110001000001000000100000000 2 p1 p2 p3 p4 p5 p6 p7 p8 p9 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 sn s dv s p dc0 p dc1 r0 r1 r2 r3 dt 0 dt 1 rs t ct e ct s 0 ct s 1 gt0 gt1 d 6 4 0 180 0 msb i/o - 1 lsb first d a t a i n2 1 1 di 9 1 00 00 0 0 0 1100000000000000010110000 2 i/o - 2 out1 out2 out3 xb xs tlr 0 tlr 1 cws 0 cws 1 h se0 h se1 h /i- 3 l /i- 4 ct p ct c il 0 il 1 uld ul0 ul1 dlc dz 0 dz 1 tes t 0 tes t 1 tes t 2 tes t 3 81 0 0 0 d 0 msb address transmitted data transmitted data address * * * * * * * * * [in1] [in2]
ps no. 6976- 29 /29 LC72151V this catalog provides information as of august, 2002. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. zoom 98.2mhz ? 118.7mhz 0.41ms 10khz 0.39ms 10khz 118.7mhz ? 98.2mhz zoom locking time (reference data) *: data here are measured using a sanyo evaluation board with the peripheral circuits and state setting shown in the sample application circuit and the LC72151V state setting examples.

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